T4L PENTIUM 4 PENTIUM D PCI EXPRESS SBC SINGLE BOARD COMPUTER , TRENTON TECHNOLOGY SYSTEM HOST BOARD SINGLE BOARD COMPUTER
SINGLE BOARD COMPUTERS & ACTIVE / PASSIVE BACKPLANES
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 T4L Technical Reference - Click Here T4L Reference Manual - Click Here SBC Support Page (drivers, etc.) - Click Here |
FEATURES
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| DESCRIPTION Chassis Plans' T4L is a graphics-class, PICMG® 1.3 system host board that offers flexibility, performance and value. The SHB supports x16, x4 and x1 PCI Express links, and a 32-bit/33MHz PCI interface to a PICMG 1.3 backplane. The T4L handles a wide range of system option cards, from the latest x16 PCI Express video cards to legacy 32-bit/33MHz PCI cards. Socket-LGA775 processor options support 32-bit and 64-bit applications, have larger L2 cache memories and some processors feature dual-core architectures. The Intel® 945G MCH and Intel® ICH7R ICH deliver advanced T4L capabilities for demanding applications. Download the T4L Datasheet here.  
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| PROCESSOR Intel® Pentium® 4 Processor at 3.0GHz to 3.8GHz* Intel® Pentium® D Processor at 2.8GHz to 3.4GHz* Intel® Celeron® D Processor at 2.93GHz to 3.33GHz* Processor Package: FC-LGA4, plugs into an LGA775 socket  *Higher
speeds as available CHIPSET The T4L's Intel® 945G chipset combines advanced video and graphics capabilities with high-bandwidth interfaces such as a dual-channel DDR2-667, 1066MHz FSB, PCI Express x16 graphics port and PCI Express x4 and x1 links to a PICMG 1.3 backplane. An Intel® ICH7R I/O Controller Hub provides eight USB 2.0 and four SATA/300 ports. The ICH7R's SATA controller supports independent DMA, Advanced Host Controller Interface (AHCI) and integrated RAID level 0, 1, 5 and 10 functionality. The I/O Controller Hub's LPC interface is routed to the board's controlled impedance connector and supports an optional I/O expansion board (Chassis Plans' IOB30) for legacy I/O and serial port communications. A x1 PCI Express (PCIe) link is also routed from the ICH7R to the controlled impedance connector to provide an additional x1 PCIe link to a PICMG 1.3 backplane when using Chassis Plans' IOB31 board. Communications between the Intel® 945G Memory Controller Hub and the Intel® ICH7R I/O Controller Hub occurs over the Direct Media Interface (DMI) at a data transfer rate of 10Gb/s in each direction. ETHERNET INTERFACES The T4L uses an internal x1 PCI Express link to connect the I/O Controller hub to a dual-port Gigabit Ethernet controller chip. This design feature enables dual 10/100/1000Base-T Ethernet interfaces on LAN 1 and LAN2. The LAN ports on the T4L have RJ-45 connectors on the I/O bracket to provide the mechanical interfaces to the Ethernet networks. The ICH7R's internal LAN Interconnect Interface (LCI) is connected to the Intel® 82562G1 Ethernet controller chip to provide an additional 10/100Base-T Ethernet interface for use on PICMG® 1.3 backplanes via the SHB's edge connector C. FOUR SERIAL ATA/300 PORTS The primary and secondary Serial ATA (SATA) ports on the T4L board support four independent SATA storage devices such as hard disks and CD-RW devices. SATA produces higher performance interfacing by providing data transfer rates up to 300MB per second on each port. The T4L's ICH7R I/O Controller hub features Intel® Matrix Storage Technology, which allows the ICH7R's SATA controller to be configured as a RAID controller supporting RAID 0, 1, 5, and 10 implementations. CACHE MEMORY (L2 AND L1) The Intel® Pentium® 4 Processor 651 and other 600 series processors feature a level two (L2) cache memory integrated on-die with Advanced Transfer Cache memory that is 8-way set associative with ECC and runs at the full processor core frequency. The L2 cache memory size is 2MB, however other Intel® Pentium® 4 processors (500 series) supported on the T4L have a 1MB L2 cache. The Intel® Pentium® D processors feature either two 1MB level two (L2) cache memories (2x1MB) or two 2MB level two (L2) cache memories (2x2MB) for a total of 2MB and 4MB L2 cache respectively. The L2 cache is integrated on-die with Advanced Transfer Cache memories that are 8-way set associative with ECC and run at the full processor core frequency. The Intel® Celeron® D processors feature a 256KB or 512KB level two (L2) cache memory. All processor options supported on the T4L have a 16KB level one (L1) data cache. DDR2-667 MEMORY The DDR2-667 memory interface is a dual-channel interface originating at the Memory Controller Hub, with each channel terminating at a DIMM module socket. The T4L supports system memory transfer rates of either 400, 533 or 667MHz using unbuffered, non-ECC, PC2-3200, PC2-4200 or PC2-5300 DIMMs. Maximum memory capacity is 4GB. When using a single PC2-5300 DIMM, the memory interface bandwidth is 5.4GB/s and using two DIMMs with equal memory capacities increases the peak memory bandwidth to 10.7GB/s. To maximize system performance and reliability Chassis Plans recommends using DIMMs that support the Serial Presence Detect (SPD) data structure. MEMORY DIMM SLOT POPULATION Chassis Plans' T4L supports two types of memory operations: Interleaved Mode - This is the mode of operation that enables the highest memory interface speed and bandwidth throughput capability. Often times this mode of operation is referred to as "dual-channel mode". Interleaved mode occurs when using two DIMM modules with equal memory capacities. The DIMM technology and device width can vary but the installed memory capacity for each channel must be equal. If different speed DIMMs are used in each channel then the slowest DIMM will determine the memory interface speed. Asymmetric Mode - From a system operational standpoint, asymmetric mode functions as a "single-channel" memory interface. Asymmetric mode occurs when using either a single DIMM module or two DIMM modules with unequal memory capacities The DIMM technology and device width can vary in each channel and if different speed DIMMs are used in each channel then the slowest DIMM will determine the memory interface speed. NOTE: Double-sided DIMMS with a x16 organization are not supported. POWER REQUIREMENTS Typical Values - 100% Stressed via MS Windows HCT's System Stress
Typical Values - System Idling In Windows XP Desktop
Tolerance for all voltages is +/- 5% and must be applied by the PICMG 1.3 backplane to edge connector C. All processors listed are Intel® Pentium® 4 except: (#) Intel® Pentium® D 940 and (*) Intel® Celeron® D 341. TEMPERATURE/ENVIRONMENT
MECHANICAL In a typical backplane, the T4L's cooling solution enables placement of option cards approximately 3.28" (60.45mm) away from the top component side of the SHB. The T4L's overall dimensions are 13.330"; (33.858cm) L x 4.976"; (12.639cm) H. The relative PICMG 1.3 SHB height off the backplane is the same as a PICMG 1.0 SBC due to the shorter PCI Express backplane connectors. |
PCI EXPRESS INTERFACES Chassis Plans' T4L graphics-class system host board provides one x16 PCI Express link on the SHB's edge connectors A and B. This x16 PCIe link is designed to support PCI Express video/graphics cards on an SHB Express(PICMG 1.3) backplane. A x4 PCI Express link and five PCI Express reference clocks are also included on edge connectors A and B. An additional x1 PCI Express link between the T4L and backplane can be provided by Chassis Plans' optional IOB31 I/O Expansion Module. The x4 and x1 PCI Express links are used on SHB Express backplanes to support PCI Express option cards and the bridge chips that provide PCI/PCI-X option card support. During system initialization the T4L automatically negotiates with the PCI Express cards connected to the PCI Express links in order to set up communication between the devices. The net result is that the T4L system host board supports communication to x1, x4, x8 and x16 PCI Express boards as well as PCI/PCI-X cards via PCI Express-to-PCI/PCI-X bridge chip technology. The T4L also provides a 32-bit/33MHz PCI bus interface on edge connector D. PCI EXPRESS CONFIGURATION AND BUS SPEED
BIOS (FLASH) The T4L uses AMIBIOS8®. The flash BIOS resides in the Firmware Hub (FWH). AMIBIOS8 contains features such as:
VIDEO INTERFACE The T4L supports three video connection options:
IOB30 EXPANSION BOARD (OPTIONAL) This optional board provides legacy I/O connections via the Super I/O controller (LPC47B272). The IOB30's I/O controller connects to the T4L's LPC Bus via the board's controlled impedance connector. The following I/O interfaces are supported by the T4L via either the IOB30 or IOB31
Operating systems exhibit certain boot-up behaviors in regards to the handling of keyboard controller functions that may necessitate the addition of the IOB30 or IOB31 to the T4L. The operating systems that Chassis Plans has tested that do not require the IOB30 or IOB31 are:
Microsoft® Windows® XP Microsoft® Windows® 2003 Server Microsoft® Windows® NT 4.0 RedHat Linux 9.0 Fedora Core 2.0 SUSE Linux 9.0 The operating systems that Chassis Plans has tested that require the IOB30 or IOB31 in order to provide required PS/2 keyboard functions are:
Sun® Solaris9.0 SCO ODT 5.05 IOB31 EXPANSION BOARD (OPTIONAL) The IOB31 supports all of the same I/O functions as the IOB30 using cable header connectors. There is no I/O plate on the IOB31. The IOB31 also provides a x4 PCI Express edge connector designed to fit into a PCI Express expansion slot on a PICMG 1.3 backplane. When used on the TML system host board, the IOB31 provides an extra x1 PCI Express link to the backplane. BATTERY Built-in lithium battery for data retention of CMOS memory. EIGHT USB INTERFACES A total of eight USB 2.0 interfaces are supported by the T4L. USB ports 0 and 1 are on the I/O bracket and ports 2, 3, 4 and 5 have header connectors on the T4L. USB ports 4 and 5 can be routed to edge connector C for use on a PICMG® 1.3 backplane. The backplane routing for USB 4 and 5 is a factory-build option. Contact Chassis Plans for ordering details. USB ports 6 and 7 are routed directly to the T4L's edge connector C AGENCY APPROVALS & INDUSTRY COMPLIANCE Designed for UL60950, CAN/CSA C22.2 No. 60950-00, EN55022:1998 Class B, EN61000-4-2:1995, EN61000-4-3:1997, EN61000-4-4:1995, EN61000-4-5:1995, EN61000-4-6:1996, EN61000-4-11:1994 STANDARDS - PCI Express Base Specification 1.0a - SHB Express System Host Board PCI Express specification - PCI Industrial Computer Manufacturers Group (PICMG®) 1.3 MEAN TIME BETWEEN FAILURES (MTBF) 196,855 POH (Power-On Hours) at 40 °C., per Bellcore |
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* Contact Chassis Plans for the latest processor speed and availability. The stated bus speed, memory and communication interface speeds are component maximums; actual system performance may vary. |
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| T4L
COMPATIBLE BACKPLANES
GRAPHICS CLASS PICMG 1.3
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| BPG6741 | 1 x16 and 2 x1 PCI Express (PCIe) slots |
| BPG6714 | 1 x16 and 1 x4/x1 PCIe slot, 1 PCIe expansion slot and 3 PCI-X/PCI slots |
| BPG6615 | 1 x16 and 4 x4 PCIe slots and 6 PCI-X/PCI slots |
| BPG6600 | 1 x16 and 1 x4/x1 PCIe slot, 1 PCIe expansion slot, 6 PCI-X/PCI slots and 4 PCI 32-bit/33MHz PCI slots |
| BPG6544 | 1 x16 and 1 x4/x1 PCIe slot, 1 PCIe expansion slot, 5 PCI-X/PCI slots, 2 32-bit/33MHz PCI slots and 2 ISA slots |
| BPG4 | 1 x16 and 2 x4/x1 PCIe slots and 1 PCIe expansion slot |
| BPG2/2 | 1 x16 PCIe slot and 2 PCI-X slots |
*Contact Chassis Plans if you do not see the backplane slot configuration needed for your application |
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T4L Technical Reference - Click Here
T4L Reference Manual - Click Here
SBC Support Page (drivers, etc.) - Click Here
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