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T4L Datasheet - Click Here T4L Technical Reference - Click Here T4L Reference Manual - Click Here SBC Support Page (drivers, etc.) - Click Here	FEATURES   Long-life Intel® Pentium® 4 Processor 651 with the Intel® 945G chipset   Dual-core processor options supported (Intel® Pentium® D)   PCI Express graphics-class SHB supports x16 video and graphics cards or ADD2 cards   Direct connect video option via the chipset's Intel® Graphics Media Accelerator 950   Compatible with the SHB Express(PICMG® 1.3) specification   Supports dual channel DDR2-667 memory, 4GB maximum   Dual Gigabit Ethernet ports plus one 10/100Base-T backplane interface   Integrated RAID 0,1,5 and 10 implementation support via four SATA/300 ports
DESCRIPTION Chassis Plans' T4L is a graphics-class, PICMG® 1.3 system host board that offers flexibility, performance and value. The SHB supports x16, x4 and x1 PCI Express links, and a 32-bit/33MHz PCI interface to a PICMG 1.3 backplane. The T4L handles a wide range of system option cards, from the latest x16 PCI Express video cards to legacy 32-bit/33MHz PCI cards. Socket-LGA775 processor options support 32-bit and 64-bit applications, have larger L2 cache memories and some processors feature dual-core architectures. The Intel® 945G MCH and Intel® ICH7R ICH deliver advanced T4L capabilities for demanding applications. Download the T4L Datasheet here.
PROCESSOR Intel® Pentium® 4 Processor at 3.0GHz to 3.8GHz* Intel® Pentium® D Processor at 2.8GHz to 3.4GHz* Intel® Celeron® D Processor at 2.93GHz to 3.33GHz* Processor Package: FC-LGA4, plugs into an LGA775 socket *Higher speeds as available CHIPSET The T4L's Intel® 945G chipset combines advanced video and graphics capabilities with high-bandwidth interfaces such as a dual-channel DDR2-667, 1066MHz FSB, PCI Express x16 graphics port and PCI Express x4 and x1 links to a PICMG 1.3 backplane. An Intel® ICH7R I/O Controller Hub provides eight USB 2.0 and four SATA/300 ports. The ICH7R's SATA controller supports independent DMA, Advanced Host Controller Interface (AHCI) and integrated RAID level 0, 1, 5 and 10 functionality. The I/O Controller Hub's LPC interface is routed to the board's controlled impedance connector and supports an optional I/O expansion board (Chassis Plans' IOB30) for legacy I/O and serial port communications. A x1 PCI Express (PCIe) link is also routed from the ICH7R to the controlled impedance connector to provide an additional x1 PCIe link to a PICMG 1.3 backplane when using Chassis Plans' IOB31 board. Communications between the Intel® 945G Memory Controller Hub and the Intel® ICH7R I/O Controller Hub occurs over the Direct Media Interface (DMI) at a data transfer rate of 10Gb/s in each direction. ETHERNET INTERFACES The T4L uses an internal x1 PCI Express link to connect the I/O Controller hub to a dual-port Gigabit Ethernet controller chip. This design feature enables dual 10/100/1000Base-T Ethernet interfaces on LAN 1 and LAN2. The LAN ports on the T4L have RJ-45 connectors on the I/O bracket to provide the mechanical interfaces to the Ethernet networks. The ICH7R's internal LAN Interconnect Interface (LCI) is connected to the Intel® 82562G1 Ethernet controller chip to provide an additional 10/100Base-T Ethernet interface for use on PICMG® 1.3 backplanes via the SHB's edge connector C. FOUR SERIAL ATA/300 PORTS The primary and secondary Serial ATA (SATA) ports on the T4L board support four independent SATA storage devices such as hard disks and CD-RW devices. SATA produces higher performance interfacing by providing data transfer rates up to 300MB per second on each port. The T4L's ICH7R I/O Controller hub features Intel® Matrix Storage Technology, which allows the ICH7R's SATA controller to be configured as a RAID controller supporting RAID 0, 1, 5, and 10 implementations. CACHE MEMORY (L2 AND L1) The Intel® Pentium® 4 Processor 651 and other 600 series processors feature a level two (L2) cache memory integrated on-die with Advanced Transfer Cache memory that is 8-way set associative with ECC and runs at the full processor core frequency. The L2 cache memory size is 2MB, however other Intel® Pentium® 4 processors (500 series) supported on the T4L have a 1MB L2 cache. The Intel® Pentium® D processors feature either two 1MB level two (L2) cache memories (2x1MB) or two 2MB level two (L2) cache memories (2x2MB) for a total of 2MB and 4MB L2 cache respectively. The L2 cache is integrated on-die with Advanced Transfer Cache memories that are 8-way set associative with ECC and run at the full processor core frequency. The Intel® Celeron® D processors feature a 256KB or 512KB level two (L2) cache memory. All processor options supported on the T4L have a 16KB level one (L1) data cache. DDR2-667 MEMORY The DDR2-667 memory interface is a dual-channel interface originating at the Memory Controller Hub, with each channel terminating at a DIMM module socket. The T4L supports system memory transfer rates of either 400, 533 or 667MHz using unbuffered, non-ECC, PC2-3200, PC2-4200 or PC2-5300 DIMMs. Maximum memory capacity is 4GB. When using a single PC2-5300 DIMM, the memory interface bandwidth is 5.4GB/s and using two DIMMs with equal memory capacities increases the peak memory bandwidth to 10.7GB/s. To maximize system performance and reliability Chassis Plans recommends using DIMMs that support the Serial Presence Detect (SPD) data structure. MEMORY DIMM SLOT POPULATION Chassis Plans' T4L supports two types of memory operations: Interleaved Mode - This is the mode of operation that enables the highest memory interface speed and bandwidth throughput capability. Often times this mode of operation is referred to as "dual-channel mode". Interleaved mode occurs when using two DIMM modules with equal memory capacities. The DIMM technology and device width can vary but the installed memory capacity for each channel must be equal. If different speed DIMMs are used in each channel then the slowest DIMM will determine the memory interface speed. Asymmetric Mode - From a system operational standpoint, asymmetric mode functions as a "single-channel" memory interface. Asymmetric mode occurs when using either a single DIMM module or two DIMM modules with unequal memory capacities The DIMM technology and device width can vary in each channel and if different speed DIMMs are used in each channel then the slowest DIMM will determine the memory interface speed. NOTE: Double-sided DIMMS with a x16 organization are not supported. POWER REQUIREMENTS Typical Values - 100% Stressed via MS Windows HCT's System Stress CPU +5V +12V +3.3V 3.2GHz# 3.90A 10.34A 3.27A 3.4GHz 3.60A 4.42A 3.27A 3.0GHz 2.64A 6.70A 3.27A 2.93GHz* 3.00A 3.59A 3.27A -12V @ <100mA Typical Values - System Idling In Windows XP Desktop CPU +5V +12V +3.3V 3.2GHz# 3.02A 3.22A 3.27A 3.4GHz 2.56A 1.53A 3.27A 3.0GHz 2.40A 2.50A 3.27A 2.93GHz* 2.25A 1.71A 3.27A -12V @ <100mA Tolerance for all voltages is +/- 5% and must be applied by the PICMG 1.3 backplane to edge connector C. All processors listed are Intel® Pentium® 4 except: (#) Intel® Pentium® D 940 and (*) Intel® Celeron® D 341. TEMPERATURE/ENVIRONMENT Operating Temperature: 0° to 45° C. Storage Temperature: -40 to 70 C. Humidity: 5% to 90% non-condensing Operating Temperature: 0° to 40° C. (with Intel Pentium D processors) The high-performance Intel® processors used on the T4L may consume over 100 Watts of power. The T4L's cooling system uses a high-reliability fan mounted to the SBC. MECHANICAL In a typical backplane, the T4L's cooling solution enables placement of option cards approximately 3.28" (60.45mm) away from the top component side of the SHB. The T4L's overall dimensions are 13.330"; (33.858cm) L x 4.976"; (12.639cm) H. The relative PICMG 1.3 SHB height off the backplane is the same as a PICMG 1.0 SBC due to the shorter PCI Express backplane connectors.	PCI EXPRESS INTERFACES Chassis Plans' T4L graphics-class system host board provides one x16 PCI Express link on the SHB's edge connectors A and B. This x16 PCIe link is designed to support PCI Express video/graphics cards on an SHB Express(PICMG 1.3) backplane. A x4 PCI Express link and five PCI Express reference clocks are also included on edge connectors A and B. An additional x1 PCI Express link between the T4L and backplane can be provided by Chassis Plans' optional IOB31 I/O Expansion Module. The x4 and x1 PCI Express links are used on SHB Express backplanes to support PCI Express option cards and the bridge chips that provide PCI/PCI-X option card support. During system initialization the T4L automatically negotiates with the PCI Express cards connected to the PCI Express links in order to set up communication between the devices. The net result is that the T4L system host board supports communication to x1, x4, x8 and x16 PCI Express boards as well as PCI/PCI-X cards via PCI Express-to-PCI/PCI-X bridge chip technology. The T4L also provides a 32-bit/33MHz PCI bus interface on edge connector D. PCI EXPRESS CONFIGURATION AND BUS SPEED PCI Express - Edge Connector A & B - One x16 link, one x4 link - Five reference clocks PCI Express - (on-board only) - Two x1 links PCI - 32-bit/33MHz System or FSB - 1066MHz, 800MHz or 533MHz BIOS (FLASH) The T4L uses AMIBIOS8®. The flash BIOS resides in the Firmware Hub (FWH). AMIBIOS8 contains features such as: Support for flash devices for BIOS upgrading Integrated support for USB mass storage devices such as USB CD-ROM, CD-RW, etc. Boot from network, USB mass storage devices, IDE or ATAPI Serial port console redirection to support headless operation (requires optional IOB30 or IOB31) SATA/ATA/ATAPI support includes 48-bit LBA addressing to support SATA/ATA/IDE hard drive capacities over 137GB VIDEO INTERFACE The T4L supports three video connection options: Direct connection via the chipset's Intel® Graphics Media Accelerator 950 with faster graphics and 3D performance A x16 PCI Express graphics port that provides 3.5 times more bandwidth than an AGP 8X interface ADD2 video and graphic cards IOB30 EXPANSION BOARD (OPTIONAL) This optional board provides legacy I/O connections via the Super I/O controller (LPC47B272). The IOB30's I/O controller connects to the T4L's LPC Bus via the board's controlled impedance connector. The following I/O interfaces are supported by the T4L via either the IOB30 or IOB31 SERIAL INTERFACE The Super I/O controller supports two full-function serial ports with independently programmable baud rates. The controller has two high-speed, NS16C550 compatible UARTs with Send/Receive 16-byte FIFOs. The IRQ for each serial port has BIOS selectable addressing. FLOPPY DRIVE INTERFACE The IOB30 supports up to two floppy disk drives in combinations of 360K to 2.88MB. KB AND PS/2 MOUSE INTERFACES The mini DIN connector located on the I/O bracket provides an external interface for a PS/2 mouse and keyboard. A "Y" adapter plugged into the mini DIN connector allows the PS/2 mouse and keyboard to share the same port. Internal PS/2 mouse and keyboard headers are also available. A self-resetting fuse protects the +5V line of the keyboard and the mouse. PARALLEL INTERFACE The parallel port interface is compatible with IBM PC/XT®, PC/AT®, PS/2TM, Enhanced Parallel Port (EPP1.7, EPP1.9) and Extended Capabilities Port (ECP) modes of operation. Both the EPP and ECP modes are IEEE 1284 compliant. The parallel port has BIOS selectable addressing. Operating systems exhibit certain boot-up behaviors in regards to the handling of keyboard controller functions that may necessitate the addition of the IOB30 or IOB31 to the T4L. The operating systems that Chassis Plans has tested that do not require the IOB30 or IOB31 are: Microsoft® Windows® 2000 Microsoft® Windows® XP Microsoft® Windows® 2003 Server Microsoft® Windows® NT 4.0 RedHat Linux 9.0 Fedora Core 2.0 SUSE Linux 9.0 The operating systems that Chassis Plans has tested that require the IOB30 or IOB31 in order to provide required PS/2 keyboard functions are: Unixware® 7.11 Sun® Solaris9.0 SCO ODT 5.05 IOB31 EXPANSION BOARD (OPTIONAL) The IOB31 supports all of the same I/O functions as the IOB30 using cable header connectors. There is no I/O plate on the IOB31. The IOB31 also provides a x4 PCI Express edge connector designed to fit into a PCI Express expansion slot on a PICMG 1.3 backplane. When used on the TML system host board, the IOB31 provides an extra x1 PCI Express link to the backplane. BATTERY Built-in lithium battery for data retention of CMOS memory. EIGHT USB INTERFACES A total of eight USB 2.0 interfaces are supported by the T4L. USB ports 0 and 1 are on the I/O bracket and ports 2, 3, 4 and 5 have header connectors on the T4L. USB ports 4 and 5 can be routed to edge connector C for use on a PICMG® 1.3 backplane. The backplane routing for USB 4 and 5 is a factory-build option. Contact Chassis Plans for ordering details. USB ports 6 and 7 are routed directly to the T4L's edge connector C AGENCY APPROVALS & INDUSTRY COMPLIANCE Designed for UL60950, CAN/CSA C22.2 No. 60950-00, EN55022:1998 Class B, EN61000-4-2:1995, EN61000-4-3:1997, EN61000-4-4:1995, EN61000-4-5:1995, EN61000-4-6:1996, EN61000-4-11:1994 STANDARDS - PCI Express Base Specification 1.0a - SHB Express System Host Board PCI Express specification - PCI Industrial Computer Manufacturers Group (PICMG®) 1.3 MEAN TIME BETWEEN FAILURES (MTBF) 196,855 POH (Power-On Hours) at 40 °C., per Bellcore
MODEL NAME: T4L MODEL# MODEL NAME SPEED* INTEL PROCESSOR NAME & NUMBER EMBEDDED S6483-052-xM T4L/3.0ST1 3.0GHz Intel® Pentium® 4 531 Processor Yes S6483-054-xM T4L/3.4ST1 3.4GHz Intel® Pentium® 4 551 Processor Yes S6483-104-xM T4L/3.4ST2 3.4GHz Intel® Pentium® 4 651 Processor Yes S6483-754-xM T4L/2.93CST 2.93GHz Intel® Celeron® D 341 Processor Yes S6483-703-xM T4L/3.2CS 3.2GHz Intel® Celeron® D 351 Processor Yes DUAL CORE PROCESSOR OPTIONS S6483-202-xM T4L/3.0DT3 3.0GHz Intel® Pentium® D 830 Processor No S6483-303-xM T4L/3.2DV4 3.2GHz Intel® Pentium® D 940 Processor No * Contact Chassis Plans for the latest processor speed and availability. The stated bus speed, memory and communication interface speeds are component maximums; actual system performance may vary.

T4L Datasheet - Click Here
T4L Technical Reference - Click Here
T4L Reference Manual - Click Here
SBC Support Page (drivers, etc.) - Click Here