Home > S6544 PCI Express Backplane

	FEATURES   14-slot from factor supports PCI-Express, PCI-X, PCI and ISA option cards   One SHB Express (PICMG 1.3) System Host Board Slot   One x16 and one x8 PCI Express Slot   One PCI-X 64-bit/133MHz Slot and Four PCI-X 64-bit/66MHz Slots   Two PCI 32-bit/33MHz Slots   Two ISA Slots   Four USB 2.0 backplane I/O connections**   Two 10/100/1000Base-T backplane Ethernet ports**
**Optional USB, Ethernet, connectivity provided by PICMG 1.3 SHB. Not all SHBs support this capability. Nominal PCB thickness: .080" Connector spacing .800" centers Mounting holes .156" diameter All dimensions are inches.
GRAPHICS-CLASS PCI EXPRESS BACKPLANE Chassis Plans' BPG6544 is a graphics-class backplane that supports a x16 PCI Express (PCIe) link from a graphics-class PICMG 1.3 compatible System Host Board to the backplane's PCIE2 slot. High-end PCI Express video and graphics cards are supported with this x16 PCIe electrical link. Chassis Plans' T4L or TML are examples of graphics-class PICMG 1.3 SHBs and with an IOB31installed these SHB's can provide a x1 PCIe link via the expansion slot to the backplane's PCIE1 slot. SHB SLOT Accepts an SHB Express (PICMG® 1.3) compliant (graphics-class) processor such as Chassis Plans' current T4L and TML system host boards. PCI EXPRESS SERIAL SLOTS PCIE2 is a x16 slot connected to the SHB with a x16 PCI Express link. PCIE1 is a x8 mechanical slot driven by a x1 PCI Express link from the PCIeS expansion slot. In order to use the PCIE1 slot a Chassis Plans IOB31 I/O expansion board must be used on Chassis Plans' T4L or TML system host board. The IOB31 enables communication between the SHB/IOB31 and the PCI Express option card in slot PCIE1. OPTIONAL USB 2.0 INTERFACES The SHB Express specification defines optional I/O routings from the SHB to the backplane. Chassis Plans' BPG6544 takes advantage of this new specification feature by providing two USB 2.0 headers capable of providing up to four USB 2.0 backplane ports. Each Chassis Plans T4L/TML System Host Board supports two USB port connections to a backplane. A factory installed option provides two additional USB port connections. Contact Chassis Plans if you are interested in this optional T4L/TML functionality. OPTIONAL ETHERNET INTERFACES Chassis Plans' BPG6544 backplane supports the optional Ethernet routing feature of the SHB Express (PICMG 1.3) specification. Two 10/100/1000Base-T Ethernet RJ-45 connectors are available for use on the backplane. Data communication performance of the backplane's Ethernet interfaces depends on the Ethernet controller hardware and configuration on the system host board. Consult your SHB Ethernet interface implementation method for details. The SHB OPTIONAL BACKPLANE I/O SUPPORT TABLE explains the backplane I/O capabilities supported by Chassis Plans' PICMG 1.3 System Host Boards. POWER CONNECTORS The BPG6544 backplane is available with a power connector suitable for use with either an ATX or EPS power supply. EXTENDED-CURRENT TERMINAL BLOCKS Three extended-current terminal blocks provide additional power capacity for power-intensive applications -- up to 80 Amps of +12V, 120 Amps of +3.3V and 80 Amps of +5V. POWER INDICATORS Surface-mount LEDs provide a convenient visual check for +5V, -5V, +5V AUX,+12V, -12V and +3.3V power connection and status. CAUTION: Never install or remove the SHB or any option card from the BPG6544 backplane if the +5V AUX LED is GREEN. If the system appears to be off and the+5V AUX LED is GREEN then you need to remove or turn-off the incoming power to the system power supply. AUXILIARY POWER CONNECTOR The +12V power connector on the BPG6544 routes auxiliary power to the SHB's edge connectors. This new capability of PICMG 1.3 compliant SHBs and backplanes eliminates the need for auxiliary power connections on the system host board. PRINTED CIRCUIT LAYERS The backplane is a six-layer, .080" thick board with three separate signal layers: +5V/+12V, +3.3V and ground. Multi-layer backplane construction provides excellent noise immunity.	PCI-X PARALLEL BUS SLOTS The five PCI-X slots on the BPG6544 are connected to the SHB via a x4 PCI Express link that drives a PCI Express-to-PCI-X bridge chip. The bridge chip provides a 64-bit/66MHz PCI-X channel to support slots A1 through A4 and a 64-bit/133MHz PCI-X channel that supports slot B1. PCI-X and universal (i.e. 5V/3.3V combo or 3.3V only) PCI option cards may be used and the bridge chips will throttle-down the bus interface speeds to match any universal PCI or PCI-X card with an interface bus speed less than 66MHz or 133MHz. PCI AND ISA PARALLEL BUS SLOTS The BPG6544 supports the optional SHB edge connector D. Edge connector D provides a 32-bit/33MHz PCI interface to drive slots SLTC1 and SLTC2. This PCI Interface also connects to a PCI-to-ISA bridge chip to support ISA slots SLTD1 and SLTD2. These slots support legacy ISA and 32-bit/33MHz PCI cards to provide a simple, cost-effective transition to the PCI Express system architecture. CONNECTING POWER The combination of new power supply technologies, soft-power control signals available via the Advanced Configuration and Power Interface (ACPI) now supported by PICMG 1.3 SHBs and auxiliary power connectors on PICMG 1.3 backplanes that deliver all of the SHBs power to the edge connectors are requiring a different approach to connecting system power. Auxiliary power connectors on the backplane are provided to help improve system Mean Time To Repair (MTTR). All power can be delivered to the SHB via the board's edge connectors. Chassis Plans' PICMG 1.3 SHBs and backplane SHB edge connector slots have ample power pins available to meet the power demands of high-performance, performance-based processor SHBs like the Chassis Plans T4L. The ATX/EPS and +12V power connectors on the BPG6544 backplane also have an ample number of power pins available to meet these demands. The system designer needs to be aware of the potential power demands of the entire system including the particular SHB to ensure that both the power supply and the power connectors in the cable harness can safely deliver the necessary power to drive the entire system. Specific implementations of ACPI signals, ATX/EPS power supply type and the operating system software will determine the specific connection method for the power supply. For example the use of the Power Good (PWRGD), Power Supply On (PSON#), Five Volt Standby (5VSB) and the Power Button (PWRBT#) ACPI or soft power control signals require the following connection method: ACPI signal usage is optional and may be turned off using the SHBs BIOS and/or signal jumpers. Specific power connections and BIOS parameters will differ according to unique system design requirements. Refer to the Appendix B (Power Connection) and Advanced Setup BIOS sections of the Chassis Plans T4L/TML Technical Reference Manual for more information.
SHB OPTIONAL BACKPLANE I/O SUPPORT TABLE
Chassis Plans ETHERNET USB SATA SHB LAN0 LAN1 USB0 USB1 USB2 USB3 SATA0 SATA1 T4L* - X1 X2 X2 X3 X3 - - TML* - X1 X2 X2 X3 X3 - - * The T4L and TML system host boards will be available in Q1, 2006. 1 The LAN1 port on the backplane will function as a 10/100Base-T Ethernet interface and the operating system may logical recognize the interface as LAN2 2 Requires a T4L/TML factory build option. The operating system may logical recognize these interfaces as USB ports 4 and 5. 3 These two USB interfaces are standard on the T4L and TML SHBs. The operating system may logical recognize these interfaces as USB ports 6 and 7.
MODEL NAME: BPG6544
MODEL# MODEL NAME DESCRIPTION S6544-003 BPG6544-E+A ATX connector with three high-current terminal blocks S6544-004 BPG6544-EPS EPS connector with three high-current terminal blocks
PCI Express Backplanes Reference Manual (3.2MB) - Click Here