MCG DUAL QUAD CORE GRAPHICS CLASS SINGLE BOARD COMPUTER , TRENTON TECHNOLOGY SYSTEM HOST BOARD SINGLE BOARD COMPUTER
SINGLE BOARD COMPUTERS & ACTIVE / PASSIVE BACKPLANES
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 MCG Datasheet - Click Here MCG Technical Reference - Click Here MCG Reference Manual in PDF - Click Here SBC Support Page - Click Here |
FEATURES
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| DESCRIPTION Chassis Plans' Graphics Class MCG series (MCGI Single Processor and MCGT Dual Processor) of PICMG® 1.3 SHBs offers a wide variety of board configurations designed to excel in the most demanding graphics-class computing applications. Dual-Core processor options provide two and Quad-Core processors provide four execution cores per processor. For dual-processor board configurations, each processor has its own independent system bus to reduce data bottlenecks while maximizing processing throughput. The four-channel memory interface features DDR2-667 FB-DIMMS with a maximum of 16GB. An extended-memory SHB configuration is available that supports up to 32GB of system memory. The processing power and configuration flexibility built into the MCG-series give system designers and their customers the best technology fit for their graphics-class PICMG 1.3 computing applications. 
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| PROCESSOR Dual-Core Intel® Xeon® Processors 5100 1.6GHz to 3.0GHz* Quad-Core Intel® Xeon® Processors 5300 1.66GHz to 2.66GHz* Processor Package: LGA771 (Socket J)  *Higher
speeds as available CHIPSET The independent system bus feature of the Intel® 5000X chipset allows each processor on an MCG-series SHB to communicate directly to the Memory Controller Hub over a dedicated 1066/1333MHz system bus. The chipset has a four-channel memory interface that supports up to 16GB of system memory on MCGT/MCGI boards and up to 32GB on MCGT-E/MCGI-E SHBs. All MCG-series SHBs provide a native x16 PCI Express™ link for use with high-end video and graphics cards. The off-board PCI Express interfaces supported by the chipset include one x4 and one x16 PCIe link routed to SHB edge connectors A and B. An additional x4 PCIe link is made available to a PICMG® 1.3 backplane via the optional IOB expansion board. The LPC bus from the Intel® 6321 ESB I/O Controller Hub (ICH) is routed to the SHB’s controlled impedance connector to provide support for legacy I/O via header connectors on the IOB30 and IOB31. The ICH on the MCG-series supports six Serial ATA/300 ports, seven USB 2.0 interfaces, one Ultra ATA/100 interface, a video controller and one Gigabit Ethernet interface available on the SHB’s edge connector C for use on a PICMG 1.3 backplane. The ICH also provides a dual-channel Ethernet PHY to support the dual 10/100/1000Base-T Ethernet ports on the SHB’s I/O plate. High-speed communications between the Intel® 5000X Memory Controller Hub and the I/O Controller Hub occur over the ESI interface and two x4 PCI Express links. THREE ETHERNET INTERFACES - 10/100/1000BASE-T The MCG-series of SHBs feature the Intel® 82563EB Dual Port adapter that connects to the I/O Controller Hub and supports two high-speed 10/100/1000Base-T Ethernet interfaces on LAN ports 1 and 2 of the SHB’s I/O bracket. RJ-45 connectors, located on the I/O bracket, provide the physical interface to the Ethernet network. A third 10/100/1000Base-T Ethernet interface is supplied to the SHB’s edge connector C for use on a PICMG 1.3 backplane. The third Ethernet interface is provided by an Intel® 82573E Ethernet controller, which is driven by a x1 PCI Express link from the board’s I/O Controller Hub. SIX SERIAL ATA/300 PORTS The integrated Serial ATA (SATA) controller on the MCG-series SHBs supports six independent SATA storage devices such as hard disks and CD-RW devices. The SATA/300 ports also enable software-driven RAID 0, 1, 5 and 10 drive array configurations for demanding drive storage and security applications. SATA technology provides lower pin counts, reduced signaling voltages, simplified cabling, CRC error detection and hot-plug support. SATA produces higher performance interfacing by providing data transfer rates up to 300MB per second on each port. CACHE MEMORY (L2 AND L1) The ECC level two (L2) cache memory is a 4MB L2 cache shared by the two processor cores on the Dual-Core Intel® Xeon® 5100 series processors. Quad-Core Intel® Xeon® 5300 series processors are constructed with two die, each of which contains two processor cores. Each die contains a 4MB L2 cache memory shared between the two processor cores. This results in a total of 8MB of L2 ECC cache memory per quad-core processor. Each processor core on the dual- and quad-core processors features a 32KB level one (L1) instruction and 32KB L1 data cache. DDR2-667/533 FB-DIMM MEMORY The DDR2-667/533 Fully-Buffered DIMM (FB-DIMM) interface is a four-channel interface originating at the Memory Controller Hub with each channel terminating at an FB-DIMM socket on the MCGT and MCGI SHBs. On the MCGT-E and MCGI-E SHBs, the four channels each terminate in two FB-DIMM sockets, for a total of eight FB-DIMMs. The SHBs use ECC registered PC2-5300 or PC2-4200 FB-DIMMs. The peak memory interface bandwidth per channel is 8.0GB/s when using PC2-5300 FB-DIMMs. The MCGT/MCGI SHBs support a maximum memory capacity of 16GB, while the MCGT-E/MCGI-E boards feature an extended memory capacity of 32GB. The extended-memory board versions require four additional FB-DIMM sockets that extend the height of the MCGT-E/MCGI-E SHBs by 0.75” (1.90cm). DDR2-667/533 FB-DIMM MEMORY SLOT POPULATION An MCG-series SHB uses industry standard 72-bit wide ECC gold finger FB-DIMM memory modules in four (MCGT/MCGI) or eight (MCGT-E/MCGI-E) 240-pin sockets. The FB-DIMMs must be PC2-4200 or PC2-5300 (DDR2-533 or DDR2-667) and comply with the JEDEC Rev 2.0 specifications. With the bracket end of the board to the right, the four FB-DIMM sockets available on the MCGT and MCGI SHBs are numbered BK0A, BK1A, BK0B and BK1B, from top to bottom. On the extended-memory MCGT-E and MCGI-E SHBs, there are an additional four FB-DIMM sockets. The upper sockets are BK2A and BK2B, from left to right, and the lower sockets are BK3A and BK3B. To maximize memory interface speed and bandwidth, and to take full advantage of the four channel memory interface of the SHB’s memory controller hub, the FB-DIMMs in socket banks 0A and 1A must be identical with respect to manufacturing, speed, timing, and organization. Likewise, FB-DIMMs used in sockets 0B and 1B must be identical. FB-DIMMs in socket banks contained within the same memory channel i.e., 0A and 2A do not need to be identical. A minimum of one 512MB FB-DIMM is required in DIMM socket BK0A. When using more that one FB-DIMM, you must populate the memory sockets in multiples of two in order to maximize the speed and performance of the memory interface. Refer to the memory population chart on the MCG-series Technical Detail web page SEVEN USB INTERFACES The MCG series of SHBs supports seven high-speed USB 2.0 ports for data transfers up to 480Mbit/sec. The SHBs also support USB 1.1 devices for data transfers at 1.2 or 1.5Mbit/sec. Two USB 2.0 interface ports are located on the SHB’s I/O bracket. An on-board header supports two USB 2.0 interfaces and three additional USB 2.0 interfaces are routed to edge connector C for use on a PICMG 1.3 backplane. WATCHDOG TIMER The U14 integrated circuit on the MCG series of SHBs supplies the watchdog timer functionality. U14 is a MAX6369 from Maxim, and the IC supports a watchdog timer disable setting plus four watchdog timer reset ranges: 100-300 milli-seconds, 1-2 seconds, 10-30 seconds and 1-3 minutes. DISABLE is the default watchdog timer setting on the SHB. POWER REQUIREMENTS Typical Values - 100% Stressed with 4GB of system memory
Typical Values - System Idling with 4GB of system memory
Tolerance for all voltages is +/- 5% and must be applied by the PICMG 1.3 backplane to edge connector C. Each 1GB of additional FB-DIMM system memory typically draws an additional 0.5A of +12V power Values stated were determined using the MCGT-E board version #Quad-core processor |
PCI
EXPRESS™ INTERFACES Chassis Plans' graphics-class MCG series of SHBs provides one x16 designed to support a high-end PCI Express video and graphics card. The SHB’s x4 PCIe operates as either a x4 link or can be divided into four x1 PCIe links on the backplane. These links, along with the PCI Express reference clocks, are routed to SHB edge connectors A and B. Chassis Plans' optional IOB31 module, part number 6474-000, may be used to provide an additional x4 PCIe link to the backplane. The PCI Express links support PCI Express option cards and bridge chips that provide PCI/PCI-X option card functionality. PCI Express auto-negotiation capability is supported on the MCG series of SHBs and enables communications to x1, x4, x8 and x16 PCI Express cards as well as PCI/PCI-X cards via PCI Express-to-PCI/PCI-X bridge technology on a PICMG 1.3 backplane. PCI EXPRESS™ CONFIGURATION AND BUS SPEED
SUPER XGA VIDEO INTERFACE Chassis Plans MCG-series SHBs are equipped with the ATI® ES1000 video controller. The external memory chip used with the ES1000 provides 16MB of on-board video memory. The video controller supports pixel resolutions up to 1280 x 1024 (SXGA). Software drivers are available for popular operating systems. BIOS (FLASH) The MCG-series boards use AMIBIOS8®; the flash BIOS resides in the SHB’s Firmware Hub (FWH). AMIBIOS8 contains features such as:
IOB30/IOB31 EXPANSION BOARDS (OPTIONAL) These optional boards provide legacy I/O connections via the Super I/O controller (LPC47B272). The I/O controller on an IOB30/31 connects to the SHB’s LPC Bus via the board’s controlled impedance connector. The following I/O interfaces are supported by the MCG-series boards via either the IOB30 or IOB31:
Operating systems exhibit certain boot-up behavior with regard to the handling of keyboard controller functions that may necessitate the addition of the IOB30 or IOB31 to an MCG-series SHB. The operating systems that Chassis Plans has tested that do not require the IOB30 or IOB31 are:
Microsoft® Windows® 2000 Microsoft® Windows® XP 64-bit & 32-bit Microsoft® Windows® 2003 Server 64-bit & 32-bit
RedHat Enterprise Linux (RHEL) V4.0 AS 64-bit & 32-bit Fedora Core 6.0 64-bit & 32-bit SUSE Linux 9.0 Linux Enterprise Server 64-bit & 32-bit Sun® Solaris™ 10.0 MECHANICAL The cooling solution used on the MCG-series SHBs enables placement of option cards approximately 2.77” (70.36mm) away from the top component side of the SHB. The standard-memory versions of the SHBs (MCGT and MCGI) have overall dimensions of 13.330” (33.858cm) L x 4.976” (12.639cm) H. The relative PICMG 1.3 SHB height off the backplane is the same as a PICMG 1.0 SBC due to the shorter PCI Express backplane connectors. The extended-memory versions, models MCGT-E and MCGI-E, have overall dimensions of 13.330” (33.858cm) L x 5.726” (14.544cm) H. BATTERY Built-in lithium battery for data retention of CMOS memory. TEMPERATURE/ENVIRONMENT
AGENCY APPROVALS & INDUSTRY COMPLIANCE Designed for UL60950, CAN/CSA C22.2 No. 60950-00, EN55022:1998 Class B, EN61000-4-2:1995, EN61000-4-3:1997, EN61000-4-4:1995, EN61000-4-5:1995, EN61000-4-6:1996, EN61000-4-11:1994 STANDARDS - PCI Express™ Base Specification 1.0a - SHB Express™ System Host Board PCI Express specification - PCI Industrial Computer Manufacturers Group (PICMG®) 1.3 MEAN TIME BETWEEN FAILURES (MTBF) 186,261 POH (Power-On Hours) at 40°C., per Bellcore |
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* Contact Chassis Plans for the latest processor speed and availability. The stated bus speed, memory and communication interface speeds are component maximums; actual system performance may vary. |
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MCG Technical Reference - Click Here MCG Reference Manual in PDF - Click Here SBC Support Page (drivers, etc.) - Click Here |
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