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TQ9 Datasheet - Click
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FEATURES
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Chassis Plans' TQ9 is a graphics-class, PICMG® 1.3 single board computer (i.e. system host board) that supports a wide variety of single-, dual- and quad-core Intel® processors. New TQ9 I/O interface capabilities include an audio codec interface, two eSATA connections to the backplane and a dozen USB interfaces. The Intel® Q35 MCH and Intel® ICH9DO ICH deliver advanced features like a 1333MHz system bus and SATA RAID. Plugging the TQ9 into a PICMG 1.3 graphics-class backplane enhances system design flexibility. A system designed with the TQ9 supports option cards from x16 PCI Express to legacy 32-bit/33MHz PCI cards. |
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| PROCESSOR Intel® Core™ 2 Processor - E8xxx, Q9xxx series Intel® Core™ 2 Duo Processor - E4xxx, E6xxx series Intel® Pentium® Dual Core Processor - E2xxx series Intel® Celeron® Processor - 4xx series Processor Package: LGA775 socket CHIPSET The Intel® Q35 Express Chipset provides an advanced internal video and graphics port along with a separate x16 PCI Express interface. A dual-channel DDR2-800 memory interface supports four DIMM sockets and up to 8GB of system memory. The TQ9's ICH9DO also provides x1 and x4 PCI Express interfaces plus a 32-bit/33MHz PCI interface. Analog and digital audio capability is built into the Chassis Plans TQ9 via the ICH9DO. ETHERNET INTERFACES The TQ9 uses an internal x1 PCI Express link to connect the I/O Controller hub to the dual-port Gigabit Ethernet controller chip. This design feature enables dual 10/100/1000Base-T Ethernet interfaces on LAN 1 and LAN2. The LAN ports have RJ-45 connectors on the I/O bracket to provide the mechanical interfaces to the Ethernet networks. PICMG® 1.3 BACKPLANE I/O INTERFACES The TQ9 enables the following PICMG 1.3 backplane I/O connectivity via the SBC's edge connector C:
The primary and secondary Serial ATA (SATA) II ports on the TQ9 board support four independent SATA storage devices such as hard disks, DVD-RW and CD-RW devices. SATA produces higher performance interfacing by providing data transfer rates up to 300MB per second on each port. The TQ9's ICH9DO I/O Controller hub features Intel® Matrix Storage Technology, which allows the ICH9DO's SATA controller to be configured as a RAID controller supporting RAID 0, 1, 5, and 10 implementations. TWELVE USB INTERFACES A total of twelve USB 2.0 interfaces are supported by the TQ9. USB ports 0 and 1 are on the I/O bracket and ports 2, 3, 4, 5, 6 and 7 have header connectors on the TQ9. USB interfaces 8,9,10 and 11 are routed directly to the TQ9's edge connector C for use on a PICMG® 1.3 backplane. DDR2-800 MEMORY The DDR2-800 interface is a dual-channel interface originating at the Memory Controller Hub, with each channel terminating at two DIMM module sockets. The TQ9 supports system memory transfer rates of 800MHz using unbuffered, non-ECC PC2-6400 DIMMs. The TQ9's four DIMM sockets support a maximum memory capacity of 8GB. When using a single PC2-6400 DIMM, the peak memory interface bandwidth is 6.4GB/s, and placing a PC2-6400 DIMM in each socket of the two memory channels produces a TQ9 theoretical peak memory bandwidth of 12.8GB/s. NOTE: All memory modules must have gold contacts. CACHE MEMORY (L2) The quad-core Intel® Core™ 2 Q9xxx series processors feature a level two (L2) cache memory capacity of 12MB (2x6MB). The dual-core Intel® Core™ 2 E8xxx series of processors support an L2 cache memory size of 6MB. The dual-core Intel® Core™ 2 Duo Processor (E6xxx and E4xxx series) feature 2MB L2 cache memories while the Intel® Pentium® Dual Core Processor - E2xxx series CPUs support an L2 cache of 1MB. The single-core Intel® Celeron® 4xx processors feature a 516KB level two (L2) cache memory. MEMORY DIMM SLOT POPULATION Chassis Plans' TQ9 supports two types of memory operations: Interleaved Mode - This is the mode of operation that enables the highest memory interface speed and bandwidth throughput capability. Often times this mode of operation is referred to as "dual-channel mode". Interleaved mode occurs when using two or four DIMM modules with equal memory capacities. The DIMM technology and device width can vary but the installed memory capacity for each channel must be equal. If different speed DIMMs are used in each channel then the slowest DIMM will determine the memory interface speed. Asymmetric Mode - From a system operational standpoint, asymmetric mode functions as a "single-channel" memory interface. Asymmetric mode occurs when using either a single DIMM module or DIMM modules with unequal memory capacities The DIMM technology and device width can vary in each channel and if different speed DIMMs are used in each channel then the slowest DIMM will determine the memory interface speed. A memory module can be installed in only one DIMM socket. If only one DIMM module is used, it must be populated in either DIMM socket BKA1 or BKB1. The TQ9's memory interface operates at maximum bandwidth with two DIMMs of the same size installed in DIMM Socket BKA1 and BKB1, but the DIMMs may differ in technology (component density) and/or device width. Populating identical DIMMs in all four DIMM sockets will also achieve maximum memory bandwidth operation. To ensure maximum system performance and reliability, Chassis Plans recommends using DIMMs that support the Serial Presence Detect (SPD) data structure. NOTE 1: Double-sided DIMMS with a x16 organization are not supported. NOTE 2: To minimize memory channel errors regardless of the type of memory module used; Chassis Plans recommends memory DIMMs with a memory clock cycle specification of ten (10). POWER REQUIREMENTS Typical Values - CPU Idle State:
Typical Values - 100% CPU Stress State:
Tolerance for all voltages is +/- 5% and must be applied by the PICMG 1.3 backplane to edge connector C. All processors listed are dual core CPUs except: (#) quad-core [Yorkfield] Intel® Core 2™ and (*) single-core Intel® Celeron®. OPERATING TEMPERATURE (Standard Cooling Solution) Operating Temperature: 0° to 60° C. (Celeron 440 CPU) Operating Temperature: 0° to 50° C. (All other processors) OPERATING TEMPERATURE (Low-profile Cooling Solution)1 Operating Temperature: 0° to 55° C. (Celeron 440 CPU) Operating Temperature: 0° to 45° C. (All dual-core processors) Operating Temperature: 0° to 40° C. (All quad-core processors) 1Contact Chassis Plans for information on ordering the TQ9 with the low profile cooling solution. OTHER ENVIRONMENTAL REQUIREMENTS Storage Temperature: -40° to 70° C. Humidity: 5% to 90% non-condensing MECHANICAL The standard cooling solution used on the TQ9 SHBs enables placement of option cards approximately 2.48" (62.99mm) away from the top component side of the SHB. An optional lower profile cooling solution is available that allows the placement of option cards approximately 2.20" (55.88mm) away from the top component side of the SHB. The TQ9's overall dimensions are 13.330" (33.858cm) L x 4.976" (12.639cm) H. The relative PICMG 1.3 SHB height off the backplane is the same as a PICMG 1.0 SBC due to the shorter PCI Express backplane connectors. |
PCI EXPRESS™ INTERFACES Chassis Plans' TQ9 graphics-class single board computer or system host board provides one x16 PCI Express link on the SBC's edge connectors A and B. A x4 PCI Express link and five PCI Express reference clocks are also included on edge connectors A and B. An additional x1 PCI Express link and reference clock between the TQ9 and backplane can be provided by Chassis Plans' optional IOB3x I/O Expansion Module. The PCI Express links are used on SHB Express backplanes to support PCI Express option cards and the bridge chips that provide PCI/PCI-X option card support. During system initialization the TQ9 automatically negotiates with the PCI Express cards connected to the PCI Express links in order to set up communication between the devices. The net result is that the TQ9 system host board supports communication to x1, x4, x8 and x16 PCI Express boards as well as PCI/PCI-X cards via PCI Express-to-PCI/PCI-X bridge chip technology. The TQ9 also provides a 32-bit/33MHz PCI bus interface on edge connector D. PCI EXPRESS™ CONFIGURATION AND BUS SPEED
Notes: 1. The x16 link may be used for external PCI Express video cards or to support general purpose PCI Express cards in conjunction with the TQ9's internal video port. 2. The x16 PCIe link on SHB edge connectors A & B can not be bifurcated into multiple PCIe links on a PICMG 1.3 backplane. 3. The x4 PCIe link on SHB edge connectors A & B may be divided into four x1 PCIe links on a PICMG 1.3 backplane. VIDEO INTERFACES The TQ9 supports three video connection options:
The TQ9 supports two Audio interface connections:
The TQ9 uses AMIBIOS8®. The flash BIOS resides in the Firmware Hub (FWH). AMIBIOS8 contains features such as:
This optional board provides legacy I/O connections via the Super I/O controller (LPC47B272). The IOB30's I/O controller connects to the TQ9's LPC Bus via the board's controlled impedance connector. The following I/O interfaces are supported by the TQ9 via either the IOB30MC or IOB31:
Operating systems exhibit certain boot-up behaviors in regards to the handling of keyboard controller functions that may necessitate the addition of the IOB30 or IOB31 to the TQ9. The operating systems that Chassis Plans has tested that do not require the IOB30MC or IOB31 are:
Microsoft® Windows® XP Professional Microsoft® Windows® 2000 Professional Microsoft® Windows® 2003 Enterprise Server RedHat Enterprise Linux 5.0 Fedora 7.0 SUSE Enterprise Linux 10.0
Previous Linux versions Built-in lithium battery for data retention of CMOS memory. WATCHDOG TIMER The programmable watchdog timer is supported directly by the I/O Controller Hub. Two operating modes, free-running and one-shot, are available with this two-stage watchdog timer. Stage one can generate IRQ, SMI or SCI, and stage two generates a programable watchdog timer reset with a total range of 1ms to 10 minutes. AGENCY APPROVALS & INDUSTRY COMPLIANCE Designed for UL60950, CAN/CSA C22.2 No. 60950-00, EN55022:1998 Class B, EN61000-4-2:1995, EN61000-4-3:1997, EN61000-4-4:1995, EN61000-4-5:1995, EN61000-4-6:1996, EN61000-4-11:1994 MEAN TIME BETWEEN FAILURES (MTBF) TBD POH (Power-On Hours) at 40 °C., per Bellcore |
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* Contact Chassis Plans for the latest processor speed and availability. The stated bus speed, memory and communication interface speeds are component maximums; actual system performance may vary. |
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| TQ9
COMPATIBLE BACKPLANES
GRAPHICS CLASS PICMG 1.3
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| BPG6741 | 1 x16 and 2 x1 PCI Express (PCIe) slots |
| BPG6714 | 1 x16 and 1 x4/x1 PCIe slot, 1 PCIe expansion slot and 3 PCI-X/PCI slots |
| BPG6615 | 1 x16 and 4 x4 PCIe slots and 6 PCI-X/PCI slots |
| BPG6600 | 1 x16 and 1 x4/x1 PCIe slot, 1 PCIe expansion slot, 6 PCI-X/PCI slots and 4 PCI 32-bit/33MHz PCI slots |
| BPG6544 | 1 x16 and 1 x4/x1 PCIe slot, 1 PCIe expansion slot, 5 PCI-X/PCI slots, 2 32-bit/33MHz PCI slots and 2 ISA slots |
| BPG4 | 1 x16 and 2 x4/x1 PCIe slots and 1 PCIe expansion slot |
| BPG2/2 | 1 x16 PCIe slot and 2 PCI-X slots |
*Contact Chassis Plans if you do not see the backplane slot configuration needed for your application |
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