FEATURES
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Not all SHBs support this capability. Nominal PCB thickness: 0.080" Connector spacing: 0.800" Mounting holes: 0.156" diameter All dimensions are inches. |
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| Four-SEGMENT PCI EXPRESS™ BACKPLANE The BP4FS6890 is a four-segment PICMG® 1.3 backplane targeted at cluster computing applications. The BP4FS6890 backplane features support for up to four server-class or graphics-class system host boards. Each backplane segment is called an SHB segment and contains one system host board slot plus multiple PCI Express option card slots. On server-class models, an SHB segment contains two x16 PCI Express mechanical slots and one x8 PCIe mechanical slot. Graphics-class backplane models feature two x16 mechanical slots where one of the slots is driven with a x16 PCIe electrical link. The BP4FS6890 backplane supports all Chassis Plans' system host boards including the high performance MCX/MCG-series featuring two, multi-core Intel® Xeon® processors and the TQ9 featuring the Intel® Core™ 2 Q9400 long-life, quad-core embedded processor. PCI EXPRESS OPTION CARD SLOTS GRAPHICS-CLASS CONFIGURATION In a graphics-class configuration of the BP4FS6890, the SHB slot in each backplane segment supports a graphics-class PICMG 1.3 system host board such as Chassis Plans MCGT. Each graphics-class SHB segment supports the segment’s x16 PCI Express (PCIe) mechanical slot with a x16 PCIe electrical link from the SHB. There is one x16 PCIe mechanical slot forwith a x4 link. SERVER-CLASS CONFIGURATION In a server-class configuration of the BP4FS6890, the SHB slot in each backplane segment supports server-class PICMG 1.3 system host boards such as the Chassis Plans' MCXT. Each server-class SHB segment supports two x16 PCI Express (PCIe) mechanical slot with a x8 PCIe electrical link from the SHB. One x16 mechanical slot is provided per segment with a x4 link. OPTIONAL ETHERNET FABRIC NETWORK Chassis Plans' BP6FS6890 backplane is available with an optional Ethernet fabric to enable the SHBs in each segment to share data and communicate information to and from the system host via the backplane's Ethernet hub port. The backplane's optional Ethernet hub switch makes this functionality possible. The Ethernet hub switch controls the SHB-to-SHB communication and the SHB's communication to the host system via the 10/100/1000Base-T Ethernet port interface. This optional backplane capability requires that the SHB support the optional Ethernet interface routing to SHB edge connector C as defined in the PICMG® 1.3 specification. The Ethernet fabric on the BP4FS6890 backplane enables many system advantages in applications that require cluster computing. Consult your SHB’s Ethernet interface implementation method for details. PRINTED CIRCUIT LAYERS The backplane is a six-layer, .080” thick board with three separate signal, power (+5V/+12V, +3.3V ) and ground layers. Multi-layer backplane construction provides excellent noise immunity. POWER INDICATORS Surface-mount LEDs provide a convenient visual check for +5V, +5V AUX,+12V, -12V and +3.3V power connection and status. CAUTION: Never install or remove an SHB or any option card from any segment when any LED is illuminated. |
POWER CONNECTION OPTIONS Auxiliary power connectors on the backplane are provided to help improve system Mean Time To Repair (MTTR). All power can be delivered to the SHBs via the board's edge connectors. Chassis Plans' PICMG 1.3 SHBs and backplane SHB edge connector slots have ample power pins available to meet the power demands of high-performance dual processor SHBs. The ATX/EPS and +12V power connectors on the B4FS6890 backplane also have an ample number of power pins available to meet these demands. The system designer needs to be aware of the potential power demands of the entire system including the particular SHB to ensure that both the power supply and the power connectors in the cable harness can safely deliver the necessary power to drive the entire system. Specific implementations of ACPI signals, ATX/EPS power supply type and the operating system software will determine the specific connection method for the power supply. For example the use of the Power Good (PWRGD), Power Supply On (PSON#), Five Volt Standby (5VSB) and the Power Button (PWRBT#) ACPI or soft power control signals require the following connection method: ACPI signal usage is optional and may be turned off using the SHBs BIOS and/or signal jumpers. Specific power connections and BIOS parameters will differ depending on unique system design requirements. Refer to the Appendix B (Power Connection) and Advanced Setup BIOS sections found in the Technical Reference Manual for your specific Chassis Plans system host board for more information. |
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Note: Chassis Plans' SLT and SLI will not support the Ethernet fabric option on the BP4FS6890 backplane
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PCI Express Backplanes Reference Manual (3.2MB) - Click Here |
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